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Events

Talks, Workshops &
IEEE Sessions

Active speaker in the VLSI and semiconductor community — workshops, tech talks, and IEEE sessions on RTL design, SoC integration, and AI chip development.

Bringing the workshop to more campuses

Upcoming

—
2026
Dates Being Finalized Workshop
Hardware Design Thinking — M. S. Ramaiah
M. S. Ramaiah Institute of Technology (MSRIT), Bangalore

After the strong response at Sai Vidya, the Hardware Design Thinking workshop is coming to MSRIT — the same full-day, hands-on format: real hardware architecture problems, whiteboard deep-dives, and the thinking routines used by working silicon engineers.

📍 MSRIT, Bengaluru · Registration opening soon
—
2026
Dates Being Finalized Workshop
Hardware Design Thinking — PES University
PES University, Bangalore

The Hardware Design Thinking workshop heads to PES University next. A full day of designing, reasoning, and defending real hardware solutions — built for students who want to think like system designers, not just write RTL.

📍 PES University, Bengaluru · Registration opening soon
Workshop Success · Sai Vidya · 11 June 2026

Hardware Design Thinking, proven in the room

The first full-day Hardware Design Thinking workshop — hosted by the IEEE CEDA Bangalore Chapter with Sai Vidya Institute of Technology — put students in front of real silicon problems: a faulty block in a pipeline, a smartphone power-on waveform, a 3×3 matrix processor. No slides-only theory — whiteboards, debate, and design defense. Here is how the room responded.

29
participants surveyed
86%
rated the workshop HIGH on average
100%
rated it helpful or better — zero negative
100%
said they had room to interact & discuss
Palash Khandale leading the Hardware Design Thinking workshop, asking 'How do you think about a hardware problem?'
“How do you think about a hardware problem?” — framing before code.
Participants working through a counter and flip-flop timing problem at the whiteboard
Whiteboard deep-dive — participants defending a design.
Working through the 3x3 matrix processor design problem
The 3×3 matrix processor challenge.
Palash Khandale recognized by IEEE CEDA and Sai Vidya faculty
Recognized by IEEE CEDA & Sai Vidya faculty.
Memento presented at the Hardware Design Thinking workshop
A memorable first edition.
93%
rated the hands-on exercises HIGH for actually improving their understanding.
93%
rated the instructors' delivery & engagement HIGH.
79%
rated the workshop HIGH for sharpening how they think through hardware design.

Co-led with Milind Parelkar — Principal Engineer, Qualcomm US · Founder, fpgadesign.io · Author of Demystifying Digital Design Interview.

View the official IEEE record →
Community

IEEE Involvement

I am an active speaker in IEEE events focused on VLSI, semiconductor design, and engineering education. My sessions focus on the gap between academic learning and real-world design practice — specifically how engineers think through trade-offs, not just how they write code.

Topics I speak on:

  • — RTL design thinking and decision-making under constraints
  • — AI chip architecture and the future of hardware-assisted intelligence
  • — SoC integration challenges and cross-team ownership
  • — Career paths in VLSI — FPGA to ASIC, design to integration
Archive

Past Sessions

6
Mar 2026
Completed IEEE CEDA
ASIC Design Beyond Theory: Industry Experience and Practice
IEEE CEDA DSCE Student Chapter · Technical Talk

A technical talk bridging the gap between academic ASIC design learning and real-world semiconductor industry practice — covering industry workflows, design challenges, verification processes, and career paths in VLSI. Delivered to students at Dayananda Sagar College of Engineering, Bengaluru.

📍 DSCE, Kumaraswamy Layout, Bengaluru · 3:30 PM – 5:00 PM
View on IEEE vTools →
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Invite me to speak or run a workshop.

Open to IEEE sessions, university workshops, and industry panels on VLSI, RTL design, and AI chip development.

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