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About

Staff Engineer.
AI Chip. VLSI Design.

9+ years of hardware engineering across ARM, Qualcomm, and Granite River Labs — AI chip development, Camera HW IP for XR/AR, SoC integration, and 5+ tape-outs in 6 years.

Summary

What I do

I am a Staff Engineer at ARM, currently working on AI chips — hardware designed to assist humans in ways that current systems cannot. The work sits at the intersection of microarchitecture, silicon constraints, and real-world deployment requirements.

Before ARM, I spent several years at Qualcomm India in the Camera HW Design team — owning RTL integration from initiation through release for XR and AR platforms, with 5+ tape-outs in 6 years.

My earlier career spans USB PD and Type-C at Granite River Labs, DSP work for satellite systems at Altran, and FPGA-based DisplayPort emulation. My experience covers the full front-end: RTL design, Hard Macro planning, Lint, CDC, synthesis readiness, and DV bring-up.

RTL Integration SoC Sign-off Camera HW IP Hard Macro CDC / Lint Area Optimization AHB / AXI USB PD / Type-C DisplayPort FPGA

RTL Integration

Own integration from initiation to release. First contact for post-delivery issues, ECOs, and corrective actions.

Hard Macro Planning

Led reduction of power-hungry hard macros through clock gating and power-collapsible restructuring.

Area Optimization

Achieved 10,000 µm² savings in ISP module datapath through parameterization with minimal DV impact.

Cross-team Ownership

Collaborates across SoC, DV, SW, and synthesis teams. Provides technical support to internal and external IP users.

Philosophy

How I see design

Design is not coding.

Coding is the final step — used to express a solution that has already been thought through. The real work happens before that: understanding the problem, defining the architecture, evaluating trade-offs, deciding what matters and what doesn't.

In real product environments, most of the effort goes into making these decisions. The actual implementation often happens toward the end, once the direction is clear.

What most engineers focus on
  • Writing RTL that passes simulation
  • Executing what's in the spec
  • Delivering blocks in isolation
What actually determines outcomes
  • Defining the architecture before the first line
  • Understanding why the spec is written that way
  • Designing for integration, not just functionality
  • Making trade-offs that hold under real constraints

There is a difference between executing a spec and defining one. Most engineers spend their careers on the first. The ones who advance are the ones who understand why.

Experience

Current role

Staff Engineer
ARM
March 2026 – Present
  • Working on AI chip development — hardware at the intersection of silicon design and intelligent systems
  • Applying deep VLSI and SoC integration experience to next-generation compute architectures
Qualcomm India · June 2021 – 2024

Where most of this was built

Senior Design Engineer — RTL Integration
Qualcomm India Pvt Ltd · Camera HW Design
June 2021 – 2024
  • Qualified all design checks: Compilation, Lint, CDC with re-convergence, and Static Power flows
  • Managed RTL integration for internal and external design team contributions end-to-end
  • Responsible for SoC sign-offs on Qualcomm's critical schedule; resolved external technical queries
  • First contact for post-delivery issues — handled ECOs and CAPAs
  • Delivered complex IPs up to 2mm² with 5+ tape-outs over 6 years
  • Led Hard Macro redesign: integrated clock gating for power efficiency, restructured high port-count macros
  • Achieved 10,000 µm² area savings in ISP module datapath via parameterized design
  • Supported DV bring-up for complete power-up/down sequences; knowledgeable about GDSC switches
  • Mentored engineers with up to 4 years of experience; led project development presentations for cross-functional teams
Career

Timeline

March 2026 – Present
Staff Engineer
ARM
AI chip development — hardware designed to assist humans at scale. Microarchitecture, silicon constraints, and real-world deployment.
June 2025 – Feb 2026
Design Engineer
Samsung Semiconductor
Semiconductor design role before moving to ARM.
June 2021 – 2024
Senior Design Engineer — RTL Integration
Qualcomm India (via Cientra Techsolutions)
Camera HW IP for XR/AR platforms. RTL integration, Hard Macro planning, 10,000 µm² area optimization, 5+ tape-outs.
Jan 2019 – Sept 2019
Design Engineer
Altran Technologies
RTL work on DSP module for satellite transceiver systems.
June 2016 – Dec 2018
Design Engineer — FPGA
Granite River Labs
FPGA-based USB-C and DisplayPort emulation. 2.5 years on USB PD and Type-C specification.
Impact

Key achievements

5+

Tape-outs

Complex IPs up to 2mm² delivered over 3 years at Qualcomm with seamless integration.

10K

µm² Area Savings

Achieved in ISP module datapath through parameterized RTL design with minimal DV rework.

3.5yr

XR/AR Camera HW

Sustained ownership of Camera HW IP for XR and AR platforms at Qualcomm.

Technical

Tools & skills

Design Tools

  • SpyGlass (Lint / CDC)
  • VCSim / ModelSim
  • Vivado (FPGA)
  • Synopsys Synthesis

HDL & Scripting

  • SystemVerilog / Verilog
  • Python Scripting
  • TCL Automation

Protocols

  • AHB / AXI (SoC Interconnect)
  • USB PD / Type-C
  • DisplayPort

Design Flows

  • RTL Integration
  • CDC with Re-convergence
  • Static Power Analysis
  • STA Awareness
  • DV Bring-up Support
Education

Academic background

Bachelor of Engineering — Electronics & Telecommunication
St. Vincent Pallotti College of Engineering, Nagpur
2015
Diploma — Electronics & Telecommunication
G. H. Raisoni Polytechnic, Nagpur
2012
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