At ARM working on AI chips.
9+ years across ARM, Qualcomm, and Granite River Labs.
VLSI design. SoC integration. 5+ tape-outs in 6 years.
IEEE speaker. Mentor for RTL and ASIC engineers.
I work on product-level RTL and SoC integration — not academic projects. My work has involved real constraints: synthesis timelines, silicon behaviour, cross-team integration, and debugging issues that only show up in the full system context.
My focus has been understanding how designs behave under real conditions, not just in simulation. That means thinking in terms of timing budgets, clock domains, power intent, and integration boundaries — before writing a single line of code.
Career, technical depth, key projects, and what I actually work on at ARM.
Working sessions for RTL and SoC engineers — focused on thinking, not templates.
Thoughts on RTL design, debugging, integration challenges, and engineering decisions.
Hardware design challenges with waveforms — RTL, microarchitecture, SoC integration. Reply via DM.
Upcoming talks, workshops, and IEEE sessions — VLSI SATA 2026 and more.
Technical depth, soft skills, wisdom from work — and the personal side of how I think and explore.
1:1 mentorship, mock interviews, technical guidance, and RTL training packages.
Sessions here fund stray rescue, medical aid, and shelter support. Every session contributes to a life.